Intel Lakefield 3D Stacked CPU Gives a Glimpse of the Future

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Intel Fellow Wilfred Gomes holds a Lakefield 3D stacked CPU, showing two sets of fine connection pads.

The way CPUs get better is changing. Traditionally, better designs take advantage of better manufacturing technology. Every year or two the transistors get smaller, so you get more of them in a chip, and that lets you do more. A modern CPU design simply couldn’t have been made 10 years ago. Now, traditional improvements are getting harder to come by, you can’t just keep making the transistors smaller forever. Something has to change, and Intel have been thinking vertically with a 3D stacked CPU design.

Lakefield is Intel’s codename for their first 3D stacked CPU, due on the market this year.  It’s an ultra-low-power mobile chip with an interesting 4+1-core design, and probably isn’t going in your desktop gaming rig any time soon. Intel have announced three upcoming laptops from Samsung, Microsoft and Lenovo that should show up with it this year. Right now, however, we have a tantalizing look at the Lakefield package.

A zoomed image of the Lakefield 3D Stacked CPU
The black rectangle in the middle is the Lakefield CPU itself, with a bigger chip on top providing memory and the two sets of solder pads down the sides. Everything but storage in the 12mmx12mm size of one regulation fingernail.

So What Is a 3D Stacked CPU?

Traditionally a CPU is just one chip. They’re certainly complex, multi-layered beasts but they’re made in one factory with a single standard production process. This has some limitations – you’re working within what the process can do, chips quickly get harder to make as they get bigger, and anything you want to add to a high performance chip incurs the full cost of doing it on a high performance process.

The industry does work around some of these limitations by separating functions off into different chips –  for example almost all computers have a separate chipset that handles things like storage and USB ports. This brings its own problems though, as moving huge amounts of data across a circuit board is difficult to do quickly or efficiently.

3D stacking takes these separated chips and connects them in the most direct way possible, right on top of one another. The shortest possible connections mean you can move more data more quickly, and that opens up more design options.

What does Lakefield look like?

Lakefield is Intel’s first 3D stacked CPU, using their Foveros technology. It avoids some of the harder problems, but is a vital step on the road. The design starts with a 22nm chipset on the lowest layer, then a Foveros die to die interconnect, then the 10nm CPU, and finally an LPDDR4 memory chip on top of it all.

Diagram of the stack of chips that make up Lakefield
Top to bottom: the LPDDR memory, the CPU die, the Foveros interconnect, the chipset die and the package that holds it all together.

The two really big challenges with these 3D stacked CPUs are the connection between chips, and cooling. Cooling is a problem because not only are lower layers insulated beneath upper layers, but those upper layers are actively heating the lower layers up. Connection is a problem because not only are the physical connections tiny but they have to go between chips that have been made with different processes. It’s no wonder then that Intel have given a codename to their Foveros die to die interconnect, and give it prominence in technical presentations. This is a difficult problem and with Lakefield, Intel are showing they can solve it.

The problem of cooling is dodged in Intel Lakefield by making it a low power mobile chip. By taking cooling out of the equation, Intel can focus on proving their Foveros technology. Higher performance chips will have to address cooling too, and you can bet it’s something a lot of hard work is going into.

What does the Intel Lakefield 3D Stacked CPU tell us about the future?

Intel Lakefield is the first 3D stacked CPU, but it won’t be the last. There are still problems to solve before high performance chips can be made like this, but the future is here and the future is three-dimensional. In coming years, high-performance CPUs will almost certainly take advantage of this technology.

The other Intel Interconnect

The Foveros interconnect used in Intel Lakefield isn’t the only technology Intel have developed to combine chips. “EMIB” – Embedded Multi-die Interconnect Bridge – is Intel’s technology to connect two chips that are next to each other, rather than on top of each other. EMIB works by using an extra chip like a literal bridge. The EMIB chip is embedded in the package, and the chips to be connected are attached on either side.

This is known as “2.5D” rather than 3D, because it’s halfway between the “true” 3D Lakefield shows and a traditional “2D” chip. Chips connected with EMIB still have a very fast connection, but are next to each other rather than on top of each other. This needs more space and doesn’t have all the benefits of full 3D stacking, but gets close and also ducks the cooling question. Intel first used EMIB for their “Kaby Lake-G” family, launched in 2018, and while Lakefield doesn’t use it EMIB is another technology we’ll be seeing more of in the coming years.

A piece of EMIB silicon next to a grain of rice
That’s a grain of rice, to show just how small an EMIB die is.  This is the ‘bridge’ that can connect two chips next to each other.

The 4+1-Core Configuration

As well as being a 3D stacked CPU, Lakefield promises an interesting “4+1-core” setup that Intel are calling “Big-Bigger”. Those who follow the mobile space will be familiar with ARM’s “big.LITTLE”, this follows the same principle but clearly Intel want us to know that they’re bigger than ARM.

The principle between these hybrid designs – be it “Big-Bigger” or “big.LITTLE” – is simple. Workloads aren’t all the same, so why should cores all be the same? Lighter workloads get a smaller, cheaper, more energy efficient core. Heavier workloads get a bigger, more expensive but stronger core. Multithreaded workloads get several of the smaller cores. The result is low power consumption, but with the performance of the strong core still being there if you need it.

We haven’t seen this kind of hybrid design on a PC before, but Intel must feel that the time is right and Windows 10 is smart enough to take full advantage. Lakefield has four low-power “Tremont” cores – which has roots in the old Atom line – and one strong “Sunny Cove” core – the successor to the venerable Skylake. All five cores are tightly integrated with a shared L3 cache.

It should be stressed that “Big-Bigger” is not a “one or the other” choice. In realistic workloads, all five cores are utilised at once. Windows can work to prioritise important tasks like a game or loading a web page on the strong “Sunny Cove” core, but the efficient “Tremont” cores can still be active and working on the same task.

While it’s aimed at energy efficiency for now, “Big-Bigger” is another technology that could easily shape the enthusiast CPUs of the future. Gamers find even now that some of the time a single thread on a single core is what limits their FPS. A future gaming CPU with this technology could have 2-4 very strong cores optimised for performance, with a larger number of more efficient cores to tackle more multithreaded things like game physics or AI.

Availability

Intel Lakefield is due to appear in consumer devices this year. Look out for an Intel Lakefield version of the Samsung Galaxy Book S, the Lenovo Thinkpad X1 fold and the Microsoft Surface Neo.

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